The present invention relates to a data processing apparatus and a method of processing data. In particular, the present invention relates to a data processing apparatus for transmitting data through an embedded clock method.
During serial data transmission, when a data signal and a clock signal are transmitted through separate signal line, there may be a time difference between transmission of the data signal and transmission of the clock signal. In order to prevent the time difference, there has been proposed an embedded clock method, in which the clock signal is overlapped with the data signal to be transmitted (refer to Patent Reference).
Patent Reference: Japanese Patent Publication No. 2009-163269
In general, when serial data is transmitted through data communication, a reception side device performs a process for converting the serial data to parallel (a serial parallel conversion). When the serial data communication is performed at a high speed, it is necessary to provide a large number of latches capable of operating a high speed clock so as to apply the serial parallel conversion to the serial data at a high speed. Accordingly, due to a delay during latching, there may be a time difference (a skew) during processing a large amount of data to be processed concurrently.
In view of the problems of the conventional technique described above, an object of the present invention is to provide a data processing apparatus capable of minimizing the skew caused by the delay during latching and the like during the data communication when data is transmitted with the embedded clock method.
Further objects and advantages of the invention will be apparent from the following description of the invention.